DS083 Datasheet, PDF (55/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
CLB/Slice Configurations
Table 19 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
implemented in one of the configurations listed. Table 20 shows the available resources in all CLBs.
Table 19: Logic Resources in One CLB
Slices
4
LUTs
8
Flip-Flops MULT_ANDs
8
8
Arithmetic &
Carry-Chains
2
SOP
Chains
2
Distributed
SelectRAM+
128 bits
Shift
Registers
128 bits
TBUF
2
Table 20: Virtex-II Pro Logic Resources Available in All CLBs
Device
CLB Array: Number Number Max Distributed
Row x
of
of
SelectRAM or Shift
Column Slices LUTs
Register (bits)
XC2VP2
16 x 22
1,408 2,816
45,056
XC2VP4
40 x 22
3,008 6,016
96,256
XC2VP7
40 x 34
4,928 9,856
157,696
XC2VP20
56 x 46
9,280 18,560
296,960
XC2VPX20
56 x 46
9,792 19,584
313,334
XC2VP30
80 x 46
13,696 27,392
438,272
XC2VP40
88 x 58
19,392 38,784
620,544
XC2VP50
88 x 70
23,616 47,232
755,712
XC2VP70
104 x 82 33,088 66,176
1,058,816
XC2VPX70
104 x 82 33,088 66,176
1,058,816
XC2VP100
120 x 94 44,096 88,192
1,411,072
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
Number
Number
Number
of
of
of SOP
Flip-Flops Carry-Chains⁽¹⁾ Chains⁽¹⁾
2,816
44
32
6,016
44
80
9,856
68
80
18,560
92
112
18,560
92
112
27,392
92
160
38,784
116
176
47,232
140
176
66,176
164
208
66,176
164
208
88,192
188
240
18 Kb Block SelectRAM+ Resources
Introduction
Virtex-II Pro devices incorporate large amounts of 18 Kb
block SelectRAM+ resources. These complement the dis-
tributed SelectRAM+ resources that provide shallow RAM
structures implemented in CLBs. Each Virtex-II Pro block
SelectRAM+ resource is an 18 Kb true dual-port RAM with
two independently clocked and independently controlled
synchronous ports that access a common storage area.
Both ports are functionally identical. CLK, EN, WE, and
SSR polarities are defined through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM+ behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
Virtex-II Pro block SelectRAM+ supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in Table 21.
Table 21: Dual- and Single-Port Configurations
16K x 1 bit
2K x 9 bits
8K x 2 bits
1K x 18 bits
4K x 4 bits
512 x 36 bits
Single-Port Configuration
As a single-port RAM, the block SelectRAM+ has access to
the 18 Kb memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
DS083 (v4.7) November 5, 2007
Product Specification
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