DS083 Datasheet, PDF (120/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II Pro
source-synchronous transmitter and receiver data-valid windows.
Table 61: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Description
Duty Cycle Distortion⁽¹⁾
Clock Tree Skew⁽²⁾
Symbol
T_{DCD_LOCAL}
T_{DCD_CLK180}
T_CKSKEW
Device
–7
–6
–5
Units
0.10
0.10
0.20
ns
All
0.10
0.11
0.13
ns
XC2VP2
0.13
0.13
0.13
ns
XC2VP4
0.13
0.13
0.13
ns
XC2VP7
0.13
0.13
0.13
ns
XC2VP20
0.20
0.21
0.22
ns
XC2VPX20
0.20
0.21
0.22
ns
XC2VP30
0.20
0.22
0.24
ns
XC2VP40
0.33
0.34
0.35
ns
XC2VP50
0.40
0.41
0.42
ns
XC2VP70
0.54
0.59
0.64
ns
XC2VPX70
0.54
0.59
0.64
ns
XC2VP100
N/A
0.79
0.87
ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by
asymmetrical rise/fall times.
T_{DCD_LOCAL} applies to cases where the dedicated path from the DCM to the BUFG is bypassed and where local (IOB) inversion is
used to provide the negative-edge clock to the DDR element in the I/O. Users must follow the implementation guidelines contained
in XAPP685 for these specifications to apply.
T_{DCD_CLK180} applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
in the I/O.
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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