DS083 Datasheet, PDF (21/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Functional Description: RocketIO Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the RocketIO
multi-gigabit transceiver. For an in-depth discussion of the
RocketIO MGT, including digital and analog design consid-
erations, refer to the RocketIO Transceiver User Guide.
RocketIO Overview
Up to twenty RocketIO MGTs are available. The MGT is
designed to operate at any baud rate in the range of
622 Mb/s to 3.125 Gb/s per channel. This includes specific
baud rates used by various standards as listed in Table 4.
Figure 10, page 11 shows a high-level block diagram of the
RocketIO transceiver and its FPGA interface signals.
Table 4: Protocols Supported by RocketIO Transceiver
Mode
Channels I/O Bit Rate
(Lanes) ⁽¹⁾
(Gb/s)
1.06
Fibre Channel
1
2.12
3.1875 ⁽²⁾
The RocketIO MGT consists of the Physical Media Attach-
ment (PMA) and Physical Coding Sublayer (PCS). The
PMA contains the 3.125 Gb/s serializer/deserializer (SER-
DES), TX/RX buffers, clock generator, and clock recovery
circuitry. The PCS contains the bypassable 8B/10B
encoder/ decoder, elastic buffers, and Cyclic Redundancy
Check (CRC) units. The encoder and decoder handle the
8B/10B coding scheme. The elastic buffers support the
clock correction (rate matching) and channel bonding fea-
tures. The CRC units perform CRC generation and check-
ing.
See Table 7, page 17, for a summary of the differences
between the RocketIO X PMA/PCS and the RocketIO
PMA/PCS.
Gigabit Ethernet
1
1.25
10Gbit Ethernet
4
3.125
Infiniband
1, 4, 12
2.5
Aurora
1, 2, 3, 4, ... 0.622 – 3.125
Custom Protocol
1, 2, 3, 4, ...
up to 3.125
Notes:
1. One channel is considered to be one transceiver.
2. Virtex-II Pro MGT can support the 10G Fibre Channel data rates of
3.1875 Gb/s across 6" of standard FR-4 PCB and one connector
(Molex 74441 or equivalent) with a bit error rate of 10^-12 or better.
PMA
Transmitter Output
The RocketIO transceiver is implemented in Current Mode
Logic (CML). A CML transmitter output consists of transis-
tors configured as shown in Figure 8. CML uses a positive
supply and offers easy interface requirements. In this con-
figuration, both legs of the driver, VP and VN, sink current,
with one leg always sinking more current than its comple-
ment. The CML output consists of a differential pair with
50Ω (or, optionally, 75Ω) source resistors. The signal swing
is created by switching the current in a common-source dif-
ferential pair.
Transmitter Termination
On-chip termination is provided at the transmitter, eliminat-
ing the need for external termination. The output driver and
termination are powered by V_TTX. This configuration uses a
CML approach with selectable 50Ω or 75Ω termination to
TXP and TXN as shown in Figure 9.
50/75Ω
VTTX
50/75Ω
V_P
V_N
V_P - V_N = V_DATA
TXP
TXN
CML Output Driver
DS083-2_66_052104
Figure 8: CML Output Configuration
ug083_33_061504
Figure 9: RocketIO Transmit Termination
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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