DS083 Datasheet, PDF (26/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
The top half of the figure shows the transmission of words
split across four transceivers (channels or lanes). PPPP,
QQQQ, RRRR, SSSS, and TTTT represent words sent over
the four channels.
The bottom-left portion of Figure 13 shows the initial situa-
tion in the FPGA’s receivers at the other end of the four
channels. Due to variations in transmission delay—espe-
cially if the channels are routed through repeaters—the
FPGA fabric might not correctly assemble the bytes into
complete words. The bottom-left illustration shows the
incorrect assembly of data words PQPP, QRQQ, RSRR,
and so forth.
In Transmitters:
Full word SSSS sent over four channels, one byte per channel
PQRS T
Channel (lane) 0
PQRS T
Channel (lane) 1
PQRS T
Channel (lane) 2
PQRS T
Channel (lane) 3
Read
In Receivers:
RXUSRCLK
PQRS T
Read
RXUSRCLK
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
Before channel bonding
After channel bonding
DS083-2_16_010202
Figure 13: Channel Bonding (Alignment)
To support correction of this misalignment, the data stream
includes special byte sequences that define corresponding
points in the several channels. In the bottom half of
Figure 13, the shaded "P" bytes represent these special
characters. Each receiver recognizes the "P" channel bond-
ing character, and remembers its location in the buffer. At
some point, one transceiver designated as the master
instructs all the transceivers to align to the channel bonding
character "P" (or to some location relative to the channel
bonding character).
After this operation, words transmitted to the FPGA fabric
are properly aligned: RRRR, SSSS, TTTT, and so forth, as
shown in the bottom-right portion of Figure 13. To ensure
that the channels remain properly aligned following the
channel bonding operation, the master transceiver must
also control the clock correction operations described in the
previous section for all channel-bonded transceivers.
Transmitter Buffer
The transmitter's buffer write pointer (TXUSRCLK) is fre-
quency-locked to its read pointer (REFCLK). Therefore,
clock correction and channel bonding are not required. The
purpose of the transmitter's buffer is to accommodate a
phase difference between TXUSRCLK and REFCLK. A
simple FIFO suffices for this purpose. A FIFO depth of four
will permit reliable operation with simple detection of over-
flow or underflow, which could occur if the clocks are not fre-
quency-locked.
RocketIO Configuration
This section outlines functions that can be selected or con-
trolled by configuration. Xilinx implementation software sup-
ports 16 transceiver primitives, as shown in Table 6.
Each of the primitives in Table 6 defines default values for
the configuration attributes, allowing some number of them
to be modified by the user. Refer to the RocketIO Trans-
ceiver User Guide for more details.
Table 6: Supported RocketIO MGT Protocol Primitives
GT_CUSTOM
Fully customizable by user
GT_FIBRE_CHAN_1 Fibre Channel, 1-byte data path
GT_FIBRE_CHAN_2 Fibre Channel, 2-byte data path
GT_FIBRE_CHAN_4 Fibre Channel, 4-byte data path
GT_ETHERNET_1 Gigabit Ethernet, 1-byte data path
GT_ETHERNET_2 Gigabit Ethernet, 2-byte data path
GT_ETHERNET_4 Gigabit Ethernet, 4-byte data path
GT_XAUI_1
10-gigabit Ethernet, 1-byte data path
GT_XAUI_2
10-gigabit Ethernet, 2-byte data path
GT_XAUI_4
10-gigabit Ethernet, 4-byte data path
GT_INFINIBAND_1 Infiniband, 1-byte data path
GT_INFINIBAND_2 Infiniband, 2-byte data path
GT_INFINIBAND_4
GT_AURORA_1 ⁽¹⁾
GT_AURORA_2 ⁽¹⁾
GT_AURORA_4 ⁽¹⁾
Infiniband, 4-byte data path
1-byte data path
2-byte data path
4-byte data path
Notes:
1. For more information on the Aurora protocol, visit
http://www.xilinx.com.
Other RocketIO Features and Notes
CRC
The RocketIO transceiver CRC logic supports the 32-bit
invariant CRC calculation used by Infiniband, FibreChannel,
and Gigabit Ethernet.
On the transmitter side, the CRC logic recognizes where the
CRC bytes should be inserted and replaces four place-
holder bytes at the tail of a data packet with the computed
CRC. For Gigabit Ethernet and FibreChannel, transmitter
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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