DS083 Datasheet, PDF (38/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
(O/T) 1
(O/T) CE
(O/T) CLK1
Shared ^SR
by all
registers REV
(O/T) CLK2
(O/T) 2
FF
LATCH
D1 ^Q1
Attribute _INIT1
INIT0
SRHIGH
SRLOW
CE
CK1
SR REV
FF1
DDR MUX
FF2
(OQ or TQ)
FF
LATCH
D2 Q2
CE
CK2
SR REV
Attribute _INIT1
INIT0
SRHIGH
SRLOW
Reset Type
SYNC
ASYNC
Figure 21: Register / Latch Configuration in an IOB Block
DS031_25_110300
VCCO
OBUF
Program
Current
Clamp
Diode
VCCO
Weak
Keeper
40KΩ –
120KΩ
VCCO
40KΩ –
120KΩ
PAD
Program
Delay
IBUF
VCCAUX = 2.5V
VCCINT = 1.5V
DS083-2_07_101801
Figure 22: LVTTL, LVCMOS, or PCI SelectIO-Ultra
Standard
Input/Output Individual Options
Each device pad has optional pull-up/pull-down resistors
and weak-keeper circuit in the LVTTL, LVCMOS, and PCI
SelectIO-Ultra configurations, as illustrated in Figure 22.
Values of the optional pull-up and pull-down resistors fall
within a range of 40 KΩ to 120 KΩ when V_CCO = 2.5V (from
2.38V to 2.63V only). The clamp diodes are always present,
even when power is not.
The optional weak-keeper circuit is connected to each user
I/O pad. When selected, the circuit monitors the voltage on
the pad and weakly drives the pin High or Low. If the pin is
connected to a multiple-source signal, the weak-keeper
holds the signal in its last state if all drivers are disabled.
Maintaining a valid logic level in this way eliminates bus
chatter. An enabled pull-up or pull-down overrides the
weak-keeper circuit.
LVCMOS25 sinks and sources current up to 24 mA. The
current is programmable (see Table 11). Drive strength and
slew rate controls for each output driver minimize bus tran-
sients. For LVDCI and LVDCI_DV2 standards, drive strength
and slew rate controls are not available.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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