DS083 Datasheet, PDF (110/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Master/Slave SelectMAP Parameters
Figure 10 is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
Virtex-II Pro Platform FPGA User Guide.
CCLK
CS_B
RDWR_B
DATA[0:7]
BUSY
3
TSMCSCC
5
T_SMCCW
1
TSMDCC
2
T_SMCCD
7
T_SMCKBY
4
T_SMCCCS
6
TSMWCC
No Write
Write
No Write
Write
ds083-3_10_012004
Figure 10: SelectMAP Mode Data Loading Sequence (Generic)
Table 48: SelectMAP Mode Write Timing Characteristics
Description
Device
Figure
References
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VPX20
DATA[0:7] setup/hold
XC2VP30
1/2
XC2VP40
XC2VP50
CCLK
XC2VP70
XC2VPX70
XC2VP100
CS_B setup/hold
3/4
RDWR_B setup/hold
5/6
BUSY propagation delay
7
Maximum start-up frequency
Maximum frequency
Maximum frequency with no handshake
Symbol
T_SMDCC/T_SMCCD
T_SMCSCC/T_SMCCCS
T_SMCCW/T_SMWCC
T_SMCKBY
F_{CC_STARTUP}
F_{CC_SELECTMAP}
F_CCNH
Value
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
6.0/0.0
6.0/0.0
7.5/0.0
7.0/0.0
7.0/0.0
12.0
50
50
50
Units
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, max
MHz, max
MHz, max
MHz, max
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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