DS083 Datasheet, PDF (59/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
18-Bit x 18-Bit Multipliers
Introduction
A Virtex-II Pro multiplier block is an 18-bit by 18-bit 2’s com-
plement signed multiplier. Virtex-II Pro devices incorporate
many embedded multiplier blocks. These multipliers can be
associated with an 18 Kb block SelectRAM+ resource or
can be used independently. They are optimized for
high-speed operations and have a lower power consump-
tion compared to an 18-bit x 18-bit multiplier in slices.
Each SelectRAM+ memory and multiplier block is tied to
four switch matrices, as shown in Figure 53.
Switch
Matrix
Switch
Matrix
Switch
Matrix
18-Kbit block
SelectRAM
Switch
Matrix
DS031_33_101000
Figure 53: SelectRAM+ and Multiplier Blocks
Association With Block SelectRAM+ Memory
The interconnect is designed to allow SelectRAM+ memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM+ and the
multiplier. Thus, SelectRAM+ memory can be used only up
to 18 bits wide when the multiplier is used, because the mul-
tiplier shares inputs with the upper data bits of the
SelectRAM+ memory.
This sharing of the interconnect is optimized for an
18-bit-wide block SelectRAM+ resource feeding the multi-
plier. The use of SelectRAM+ memory and the multiplier
with an accumulator in LUTs allows for implementation of a
digital signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits. Figure 54 shows a multiplier block.
A[17:0]
B[17:0]
Multiplier Block
MULT 18 x 18
P[35:0]
DS031_40_100400
Figure 54: Multiplier Block
Locations / Organization
Multiplier organization is identical to the 18 Kb SelectRAM+
organization, because each multiplier is associated with an
18 Kb block SelectRAM+ resource.
Table 26: Multiplier Resources
Device
Columns
XC2VP2
4
XC2VP4
4
XC2VP7
6
XC2VP20
8
XC2VP30
8
XC2VPX20
8
XC2VP40
10
XC2VP50
12
XC2VP70
14
XC2VPX70
14
XC2VP100
16
Total Multipliers
12
28
44
88
136
88
192
232
328
308
444
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to Configurable Logic Blocks (CLBs), page 35).
Global Clock Multiplexer Buffers
Virtex-II Pro devices have 16 clock input pins that can also
be used as regular user I/Os. Eight clock pads center on
both the top edge and the bottom edge of the device, as
illustrated in Figure 55.
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II Pro
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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