DS083 Datasheet, PDF(41/430 Page) Xilinx, Inc – Summary of Features

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DS083 Datasheet, PDF (41/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description

Table 12: Summary of Voltage Supply Requirements

for All Input and Output Standards

I/O Standard

VCCO

Output Input

VREF

Input

Termination Type

Output Input

LVTTL (1)

N/R

N/R

N/R

LVCMOS33 (1)

N/R

N/R

N/R

LVDCI_33 (1)

PCIX (2)

N/R Series

N/R

3.3

3.3

N/R

N/R

N/R

PCI33_3 (2)

N/R

N/R

N/R

PCI66_3 (2)

N/R

N/R

N/R

LVDS_25

N/R

N/R

N/R

LVDSEXT_25

N/R

N/R

N/R

LDT_25

N/R

N/R

N/R

ULVDS_25

BLVDS_25

N/R

N/R

N/R

Note (3)

N/R

N/R

N/R

LVPECL_25

N/R

N/R

N/R

SSTL2_I

1.25

N/R

N/R

SSTL2_II

1.25

N/R

N/R

LVCMOS25

N/R

N/R

N/R

LVDCI_25

2.5

N/R Series

N/R

LVDCI_DV2_25

N/R Series

N/R

LVDS_25_DCI

N/R

N/R

Split

LVDSEXT_25_DCI

N/R

N/R

Split

SSTL2_I_DCI

2.5 1.25

N/R

Split

SSTL2_II_DCI

1.25

Split

Split

LVDS_25_DT

N/R

N/R

N/R

LVDSEXT_25_DT

N/R

N/R

N/R

LDT_25_DT

N/R

N/R

N/R

ULVDS_25_DT

N/R

N/R

N/R

Table 12: Summary of Voltage Supply Requirements

for All Input and Output Standards (Continued)

I/O Standard

VCCO

Output Input

VREF

Input

Termination Type

Output Input

HSTL_III_18

1.1

N/R

N/R

HSTL_IV_18

1.1

N/R

N/R

HSTL_I_18

HSTL_II_18

0.9

N/R

N/R

Note (3)

0.9

N/R

N/R

SSTL18_I

0.9

N/R

N/R

SSTL18_II

0.9

N/R

N/R

LVCMOS18

N/R

N/R

N/R

LVDCI_18

1.8

N/R Series

N/R

LVDCI_DV2_18

N/R Series

N/R

HSTL_III_DCI_18

1.1

N/R

Single

HSTL_IV_DCI_18

1.8

1.1 Single Single

HSTL_I_DCI_18

0.9

N/R

Split

HSTL_II_DCI_18

0.9

Split

Split

SSTL18_I_DCI

0.9

N/R

Split

SSTL18_II_DCI

0.9

Split

Split

HSTL_III

0.9

N/R

N/R

HSTL_IV

HSTL_I

0.9

N/R

N/R

Note (3)

0.75

N/R

N/R

HSTL_II

0.75

N/R

N/R

LVCMOS15

N/R

N/R

N/R

LVDCI_15

1.5

LVDCI_DV2_15

N/R Series

N/R

N/R Series

N/R

GTLP_DCI

HSTL_III_DCI

1

Single Single

1.5

0.9

N/R

Single

HSTL_IV_DCI

0.9 Single Single

HSTL_I_DCI

0.75

N/R

Split

HSTL_II_DCI

0.75

Split

Split

GTL_DCI

1.2

1.2

0.8 Single Single

GTLP

GTL

1

N/R

N/R

N/R Note (3)

0.8

N/R

N/R

Notes:

1. See application note XAPP659 for more detailed information.

2. See application note XAPP653 for more detailed information.

3. Pin voltage must not exceed VCCO.

4. N/R = no requirement.

DS083 (v4.7) November 5, 2007

Product Specification

www.xilinx.com

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