DS083 Datasheet, PDF (122/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 64: Example Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
Speed Grade
Description
Symbol
Device
–7
–6
–5 Units
Example Data Input Set-Up and Hold Times
Relative to a Forwarded Clock Input Pin,⁽¹⁾
Using DCM and Global Clock Buffer.
Values represent an 18-bit bus located in Banks
2, 3, 6, or 7 and grouped to one Horizontal
Global Clock Line. TRACE must be used to
determine the actual values for any given
design.
For situations where clock and data inputs
conform to different standards, adjust the setup
and hold values accordingly using the values
shown in IOB Input Switching Characteristics
Standard Adjustments, page 23.
No Delay
Global Clock and IFF⁽²⁾ with DCM
T_{PSDCM_0}/T_{PHDCM_0} XC2VP2 0.23/0.39 0.21/0.42 0.21/0.42 ns
XC2VP4 0.26/0.37 0.24/0.40 0.24/0.41 ns
XC2VP7 0.18/ 0.36 0.18/ 0.40 0.18/ 0.41 ns
XC2VP20 0.14/ 0.41 0.13/ 0.42 0.12/ 0.44 ns
XC2VPX20 0.14/ 0.41 0.13/ 0.42 0.12/ 0.44 ns
XC2VP30 0.29/ 0.25 0.31/ 0.24 0.31/ 0.24 ns
XC2VP40 0.25/ 0.30 0.26/ 0.29 0.27/ 0.29 ns
XC2VP50 0.18/ 0.36 0.18/ 0.38 0.17/ 0.39 ns
XC2VP70 0.18/ 0.37 0.18/ 0.38 0.18/ 0.38 ns
XC2VPX70 0.18/ 0.37 0.18/ 0.38 0.18/ 0.38 ns
XC2VP100 N/A 0.18/ 0.33 0.19/ 0.37 ns
Notes:
1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case duty-cycle distortion using CLK0 and CLK180, T_{DCD_CLK180}
Package skew is not included in these measurements.
2. IFF = Input Flip-Flop
Source Synchronous Timing Budgets
This section describes how to use the parameters provided
in the Source-Synchronous Switching Characteristics sec-
tion to develop system-specific timing budgets. The follow-
ing analysis provides information necessary for determining
Virtex-II Pro contributions to an overall system timing analy-
sis; no assumptions are made about the effects of
Inter-Symbol Interference or PCB skew.
Virtex-II Pro Transmitter Data-Valid Window (T_X)
T_X is the minimum aggregate valid data period for a
source-synchronous data bus at the pins of the device and
is calculated as follows:
T_X = Data Period - [Jitter⁽¹⁾ + Duty Cycle Distortion⁽²⁾ +
TCKSKEW⁽³⁾ + TPKGSKEW⁽⁴⁾]
Notes:
1. Jitter values and accumulation methodology to be provided in
a future release of this document. The absolute period jitter
values found in the DCM Timing Parameters section of the
particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.
2. This value depends on the clocking methodology used. See
Note1 for Table 61.
3. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
4. These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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