DS083 Datasheet, PDF (64/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
CLKIN
CLKOUT_PHASE_SHIFT
= NONE
CLKFB
CLKIN
CLKOUT_PHASE_SHIFT
= FIXED
CLKFB
(PS/256) x PERIODCLKIN
(PS negative)
(PS/256) x PERIODCLKIN
(PS positive)
CLKIN
CLKOUT_PHASE_SHIFT
= VARIABLE
CLKFB
(PS/256) x PERIODCLKIN
(PS negative)
(PS/256) x PERIODCLKIN
(PS positive)
Figure 63: Fine-Phase Shifting Effects
DS031_48_110300
Two separate components of the phase shift range must be
understood:
• PHASE_SHIFT attribute range
• FINE_SHIFT_RANGE DCM timing parameter range
The PHASE_SHIFT attribute is the numerator in the following
equation:
Phase Shift (ns) = (PHASE_SHIFT/256) * PERIOD_CLKIN
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the FINE_SHIFT_RANGE component, which represents
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under DCM Tim-
ing Parameters in Virtex-II Pro and Virtex-II Pro X Platform
FPGAs: DC and Switching Characteristics.
Absolute range (fixed mode) = ± FINE_SHIFT_RANGE
Absolute range (variable mode) = ± FINE_SHIFT_RANGE/2
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the PHASE_SHIFT value never changes after configu-
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
Taking both of these components into consideration, the fol-
lowing are some usage examples:
• If PERIOD_CLKIN = 2 * FINE_SHIFT_RANGE, then
PHASE_SHIFT in fixed mode is limited to ± 128, and in
variable mode it is limited to ± 64.
• If PERIOD_CLKIN = FINE_SHIFT_RANGE, then
PHASE_SHIFT in fixed mode is limited to ± 255, and in
variable mode it is limited to ± 128.
• If PERIOD_CLKIN ≤ 0.5 * FINE_SHIFT_RANGE, then
PHASE_SHIFT is limited to ± 255 in either mode.
Operating Modes
The frequency ranges of DCM input and output clocks
depend on the operating mode specified, either
low-frequency mode or high-frequency mode, according to
Table 30. For actual values, see Virtex-II Pro and
Virtex-II Pro X Platform FPGAs: DC and Switching Charac-
teristics. The CLK2X, CLK2X180, CLK90, and CLK270 out-
puts are not available in high-frequency mode.
High or low-frequency mode is selected by an attribute.
Table 30: DCM Frequency Ranges
Low-Frequency Mode
High-Frequency Mode
Output Clock
CLKIN Input
CLK Output
CLKIN Input
CLK Output
CLK0, CLK180
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF
CLK90, CLK270
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF
NA
NA
CLK2X, CLK2X180
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF
NA
NA
CLKDV
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF
CLKFX, CLKFX180
CLKIN_FREQ_FX_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF CLKOUT_FREQ_FX_HF
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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