DS083 Datasheet, PDF (13/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Functional Description: RocketIO X Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the RocketIO X
multi-gigabit transceiver. For an in-depth discussion of the
RocketIO X MGT, including digital and analog design con-
siderations, refer to the RocketIO X Transceiver User
Guide.
See Table 7, page 17, for a summary of the differences
between the RocketIO X PMA/PCS and the RocketIO
PMA/PCS.
Figure 4, page 3 shows a high-level block diagram of the
RocketIO X transceiver and its FPGA interface signals.
RocketIO X Overview
Either eight or twenty RocketIO X MGTs are available on
the XC2VPX20 and XC2VPX70 devices, respectively. The
XC2VPX20 MGT is designed to operate at any baud rate in
the range of 2.488 Gb/s to 6.25 Gb/s per channel. This
includes specific baud rates used by various standards as
listed in Table 1. The XC2VPX70 MGT operates at a fixed
4.25 Gb/s per channel.
The RocketIO X MGT consists of the Physical Media
Attachment (PMA) and Physical Coding Sublayer (PCS).
The PMA contains the 6.25 Gb/s serializer/deserializer
(SERDES), TX/RX buffers, clock generator, and clock
recovery circuitry. The RocketIO X PCS has been signifi-
cantly updated relative to the RocketIO PCS. In addition to
the existing RocketIO PCS features, the RocketIO X PCS
features 64B/66B encoder/decoder/scrambler/descrambler
and SONET compatibility.
Table 1: Communications Standards Supported by
RocketIO X Transceiver⁽²⁾
Mode
Channels I/O Bit Rate
(Lanes) ⁽¹⁾
(Gb/s)
SONET OC-48
1
2.488
PCI Express
1, 2, 4, 8, 16
2.5
Infiniband
1, 4, 12
2.5
XAUI (10-Gb Ethernet)
4
3.125
XAUI
(10-Gb Fibre Channel)
4
3.1875
Aurora (Xilinx protocol)
1, 2, 3, 4,... 2.488 to 6.25
Custom Mode
1, 2, 3, 4,... 2.488 to 6.25
Notes:
1. One channel is considered to be one transceiver.
2. XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
PMA
Transmitter Output
The RocketIO X transceiver is implemented in Current
Mode Logic (CML). A CML transmitter output consists of
transistors configured as shown in Figure 2. CML uses a
positive supply and offers easy interface requirements. In
this configuration, both legs of the driver, VP and VN, sink
current, with one leg always sinking more current than its
complement. The CML output consists of a differential pair
with 50Ω source resistors. The signal swing is created by
switching the current in a common-source differential pair.
Transmitter Termination
On-chip termination is provided at the transmitter, eliminat-
ing the need for external termination. The output driver and
termination are powered by V_TTX at 1.5V. This configuration
uses a CML approach with 50Ω termination to TXP and
TXN as shown in Figure 3.
VTTX (1.5V)
50Ω
50Ω
V_P
V_N
V_P - V_N = V_DATA
TXP
CML Output Driver
DS083-2_66_052104
Figure 2: CML Output Configuration
TXN
ug083_34_050704
Figure 3: RocketIO X Transmit Termination
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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