DS083 Datasheet, PDF (115/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
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Table 53: Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
Speed Grade
Description
Symbol
Device
-7
-6
-5
Units
Input Setup and Hold Time Relative to
Global Clock Input Signal for LVCMOS25
Standard.
For data input with different standards,
adjust the setup time delay by the values
shown in IOB Input Switching
Characteristics Standard Adjustments,
page 23.
Full Delay
Global Clock and IFF without DCM
T_PSFD/T_PHFD
ns
XC2VP2 1.80/–0.44 1.85/–0.41 1.96/–0.43
XC2VP4 1.82/–0.53 1.83/–0.31 1.90/–0.29
ns
XC2VP7 1.80/–0.34 1.81/–0.24 1.88/–0.19
ns
XC2VP20 1.76/–0.24 1.83/–0.17 1.92/–0.15
ns
XC2VPX20 1.76/–0.24 1.83/–0.17 1.92/–0.15
ns
XC2VP30 1.75/–0.22 1.92/–0.26 1.99/–0.23
ns
XC2VP40 2.25/–0.54 2.40/–0.56 2.49/–0.54
ns
XC2VP50 2.93/–1.02 2.98/–0.93 3.00/–0.83
ns
XC2VP70 2.79/–0.72 2.79/–0.55 2.78/–0.41
ns
XC2VPX70 2.79/–0.72 2.79/–0.55 2.78/–0.41
ns
XC2VP100
N/A
5.58/–2.35 5.60/–2.35
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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