DS083 Datasheet, PDF (256/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 — XC2VP20, XC2VP30, XC2VP40, and XC2VP50
Bank
Pin Description
Pin
Number
N/A
GND
AG8
N/A
GND
AG12
N/A
GND
AG15
N/A
GND
AG20
N/A
GND
AG23
N/A
GND
AG27
N/A
GND
J34
N/A
GND
AH7
N/A
GND
AH28
N/A
GND
AJ6
N/A
GND
AJ29
N/A
GND
AK5
N/A
GND
AK12
N/A
GND
AK23
N/A
GND
AK30
N/A
GND
AL4
N/A
GND
AL31
N/A
GND
AM1
N/A
GND
AM2
N/A
GND
AM10
N/A
GND
AM16
N/A
GND
AM19
N/A
GND
AM25
N/A
GND
AM33
N/A
GND
AM34
N/A
GND
AN1
N/A
GND
AN34
Notes:
1. See Table 4 for an explanation of the signals available on this pin.
XC2VP20
No Connects
XC2VP30 XC2VP40
XC2VP50
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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