DS083 Datasheet, PDF (124/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Date
12/03/02
01/20/03
03/24/03
05/27/03
05/27/03
(cont’d)
Version
2.5
2.6
2.7
2.8
2.8
(cont’d)
Revision
Updated parametric information in:
• Table 1: Correct lower limit of voltage range of V_IN and V_TS from –0.5V to –0.3V for
3.3V.
• Table 2: Add footnote (2) regarding V_CCAUX voltage droop. Renumbered other notes.
• Table 12: Add waveform diagrams (Figure 1 and Figure 2) illustrating DV_OUT
(single-ended) and DV_PPOUT (differential).
• Table 23: Indicate REFCLK upper frequency limitation; relate REFCLK parameters to
REFCLK2, BREFCLK, and BREFCLK2; correct T_RCLK and T_FCLK values and unit of
measurement.
• Table 57: Add qualifying footnote to CLKOUT_DUTY_CYCLE_DLL.
Updated parametric information in:
• Table 12: Correct DV_IN Min (200 mV to 175 mV) and DV_IN Max (1000 mV to 2000 mV).
• Table 23: Correct T_RCLK /T_FCLK Typ (400 ps to 600 ps) and Max (600 ps to 1000 ps).
Add footnote (2) to qualify Max T_GJTT parameter.
• Table 56: Correct hyperlink in footnote (1) to point directly to Answer Record 13645.
• Move clock parameters from Table 18, Table 19, Table 20, and Table 21 to Table 16.
• Added/updated timing parameters from speedsfile v1.76.
• Table 2: Delete first table footnote and renumber all others.
• Table 3: Add "sample-tested" to I_L. Remove "Device" column, unnecessary.
• Table 8: Update V_OCM (Typ) to 1.250V.
• Table 10: Update LVPECL_25 DC parameters.
• Table 23: Update F_GCLK frequency ranges. Break out T_GJTT by operating speed.
• Table 27: Update F_GTX frequency ranges. Correct T_DJ to 0.17 UI, T_RJ to o.18 UI.
• Table 36: Update V_REF (Typ) for HSTL Class I/II from 1.08V to 0.90V.
• Table 40, Table 41: Correct parameter name "CE input (WS)" to "SR input".
• Table 61: Break out T_{DCD_CLK0} by device type.
• Updated time and frequency parameters as per speedsfile v1.78.
• Table 3: Added values for I_REF, I_L, I_RPU, I_RPD
• Corrected I_CCINTQ (Table 4) and I_CCINTMIN (Table 5) for XC2VP20 to 600 mA.
• Table 4: Updated/Added Typ and Max quiescent current values for XC2VP7 and
XC2VP20. Added footnote specifying parameters are for Commercial Grade parts.
• Table 5: Added footnote specifying parameters are for Commercial Grade parts.
• Table 6: Corrected V_IH (Max) for LVTTL and LVCMOS33 standards from 3.6V to 3.45V.
Changed V_IL (Min) for all standards to –0.2V. Corrected V_IL (Max) for LVCMOS15 and
LVCMOS18 from 20% V_CCO to 30% V_CCO.
• Table 10: Corrected LVPECL_25 Min and Max values for V_IH and V_IL. Added
explanatory text above table.
• Table 13 and Table 14 (pin-pin and reg-reg performance): Changed device specified
from XC2VP7FF672-6 to XC2VP20FF1152-6.
• Table 15: Updated to show devices XC2VP7 and XC2VP20 as Preliminary for the -6
speed grade and Production for the -5 speed grade.
• Removed former Table 32, Standard Capacitive Loads.
• Table 49: Updated T_TAPTCK from 4.0 ns to 5.5 ns.
• Table 56: Modified footnote referenced at CLKFX/CLKFX180 to point to the online
Jitter Calculator.
• Added Figure 6 and accompanying procedure for measuring standard adjustments.
• Table 1: Footnote (2) rewritten to specify “one or more banks.”
• Table 54: Some DCM parameters were erroneously missing from v2.8 (single-module
version) due to a document compilation error. The concatenated full data sheet version
was not affected. These parameters have been restored.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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