DS083 Datasheet, PDF (66/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
• The double lines route signals to every first or second
block away in all four directions. Organized in a
staggered pattern, double lines can be driven only at
their endpoints. Double-line signals can be accessed
either at the endpoints or at the midpoint (one block
from the source).
• The direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.
• The fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.
Dedicated Routing
In addition to the global and local routing resources, dedi-
cated signals are available.
• There are eight global clock nets per quadrant. (See
Global Clock Multiplexer Buffers, page 48.)
• Horizontal routing resources are provided for on-chip
3-state buses. Four partitionable bus lines are provided
per CLB row, permitting multiple buses within a row.
(See 3-State Buffers, page 43.)
• Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
output signals vertically to the adjacent slice. (See
CLB/Slice Configurations, page 44.)
• One dedicated SOP chain per slice row (two per CLB
row) propagate ORCY output logic signals horizontally
to the adjacent slice. (See Sum of Products, page 42.)
• One dedicated shift-chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See Shift Registers, page 39.)
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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