DS083 Datasheet, PDF (8/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Virtex-II Pro / Virtex-II Pro X Device/Package Combinations and Maximum I/Os
Offerings include ball grid array (BGA) packages with
1.0 mm pitch. In addition to traditional wire-bond intercon-
nect (FG/FGG packages), flip-chip interconnect (FF pack-
ages) is used in some of the BGA offerings. Flip-chip
interconnect construction supports more I/Os than are pos-
sible in wire-bond versions of similar packages, providing a
high pin count and excellent power dissipation.
The device/package combination table (Table 3) details the
maximum number of user I/Os and RocketIO / RocketIO X
MGTs for each device and package using wire-bond or
flip-chip technology.
The FF1148 and FF1696 packages have no RocketIO
transceivers bonded out. Extra SelectIO-Ultra resources
occupy available pins in these packages, resulting in a
higher user I/O count. These packages are available for the
XC2VP40, XC2VP50, and XC2VP100 devices only.
The I/Os per package count includes all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD), VBATT, and the RocketIO / RocketIO X
transceiver pins.
Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os
FG256/ FG456/
Package⁽¹⁾ FGG256 FGG456 FG676
FF672
FF896 FF1152 FF1148 FF1517 FF1704
FF1696
Pitch (mm) 1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
Size (mm) 17 x 17 23 x 23 26 x 26 27 x 27 31 x 31 35 x 35 35 x 35 40 x 40 42.5 x 42.5 42.5 x 42.5
XC2VP2 140 / 4
156 / 4
204 / 4
XC2VP4 140 / 4
248 / 4
348 / 4
XC2VP7
248 / 8
396 / 8
396 / 8
XC2VP20
404 / 8
556 / 8
564 / 8
XC2VPX20
552 / 8⁽²⁾
XC2VP30
416 / 8
556 / 8
644 / 8
XC2VP40
416 / 8
692 / 12
804 / 0⁽³⁾
XC2VP50
692 / 16
812 / 0⁽³⁾ 852 / 16
XC2VP70
964 / 16 996 / 20
XC2VPX70
992 / 20⁽²⁾
XC2VP100
1,040 / 20 1,164 / 0⁽³⁾
Notes:
1. Wirebond packages FG256, FG456, and FG676 are also available in Pb-free versions FGG256, FGG456, and FGG676. See Virtex-II Pro Ordering
Examples for details on how to order.
2. Virtex-II Pro X device is equipped with RocketIO X transceiver cores.
3. The RocketIO transceivers in devices in the FF1148 and FF1696 packages are not bonded out to the package pins.
Maximum Performance
Maximum performance of the RocketIO / RocketIO X transceiver and the PowerPC processor block varies, depending on
package style and speed grade. See Table 4 for details. Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching
Characteristics contains the rest of the FPGA fabric performance parameters.
Table 4: Maximum RocketIO / RocketIO X Transceiver and Processor Block Performance
Device
RocketIO X Transceiver FlipChip (FF)
-7 ⁽¹⁾
N/A
Speed Grade
-6
6.25 ⁽³⁾
-5
4.25 ⁽³⁾
Units
Gb/s
RocketIO Transceiver FlipChip (FF)
3.125
3.125
2.0
Gb/s
RocketIO Transceiver Wirebond (FG)
PowerPC Processor Block
2.5
2.5
2.0
400 ⁽²⁾
350 ⁽²⁾
300
Gb/s
MHz
Notes:
1. -7 speed grade devices are not available in Industrial grade.
2. IMPORTANT! When CPMC405CLOCK runs at speeds greater than 350 MHz in -7 Commercial grade dual-processor devices, or greater than
300 MHz in -6 Industrial grade dual-processor devices, users must implement the technology presented in XAPP755, “PowerPC 405 Clock Macro for
-7(C) and -6(I) Speed Grade Dual-Processor Devices.” Refer to Table 1 to identify dual-processor devices.
3. XC2VPX70 is only available at fixed 4.25 Gb/s baud rate.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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