DS083 Datasheet, PDF (56/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
nally in user logic. In such cases, the width is viewed as
8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored
and behave exactly as the other bits, including the timing
parameters. Video applications can use the 9-bit ratio of
Virtex-II Pro block SelectRAM+ memory to advantage.
Each block SelectRAM+ cell is a fully synchronous memory
as illustrated in Figure 47. Input data bus and output data
bus widths are identical.
18-Kbit Block SelectRAM
DI
DIP
ADDR
WE
EN
SSR
CLK
DO
DOP
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM+ has
access to a common 18 Kb memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Table 22 illustrates the different configurations available on
ports A and B.
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kb block is accessible
from port A or B. If both ports are configured in either 16K x
1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the 16 K-bit
block is accessible from Port A or Port B. All other configu-
rations result in one port having access to an 18 Kb memory
block and the other port having access to a 16 K-bit subset
of the memory block equal to 16 Kbs.
DS031_10_102000
Figure 47: 18 Kb Block SelectRAM+ Memory in
Single-Port Mode
Table 22: Dual-Port Mode Configurations
Port A
16K x 1
16K x 1
Port B
16K x 1
8K x 2
Port A
8K x 2
8K x 2
Port B
8K x 2
4K x 4
Port A
4K x 4
4K x 4
Port B
4K x 4
2K x 9
Port A
2K x 9
2K x 9
Port B
2K x 9
1K x 18
Port A
1K x 18
1K x 18
Port B
1K x 18
512 x 36
Port A
512 x 36
Port B
512 x 36
16K x 1
4K x 4
8K x 2
2K x 9
4K x 4
1K x 18
2K x 9
512 x 36
16K x 1
2K x 9
8K x 2
1K x 18
4K x 4
512 x 36
16K x 1
1K x 18
8K x 2
512 x 36
16K x 1
512 x 36
DS083 (v4.7) November 5, 2007
Product Specification
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