DS083 Datasheet, PDF (158/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FG676/FGG676 Fine-Pitch BGA Package
As shown in Table 7, XC2VP20, XC2VP30, and XC2VP40 Virtex-II Pro devices are available in the FG676/FGG676
fine-pitch BGA package. The pins in these devices are the same, except for the differences shown in the "No Connects"
column. Following this table are the FG676/FGG676 Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40
No Connects
Bank
Pin Description
Pin Number
XC2VP20 XC2VP30 XC2VP40
0
IO_L01N_0/VRP_0
E5
0
IO_L01P_0/VRN_0
D5
0
IO_L02N_0
E6
0
IO_L02P_0
D6
0
IO_L03N_0
G7
0
IO_L03P_0/VREF_0
F7
0
IO_L05_0/No_Pair
E7
0
IO_L06N_0
D7
0
IO_L06P_0
C7
0
IO_L07N_0
H8
0
IO_L07P_0
G8
0
IO_L09N_0
F8
0
IO_L09P_0/VREF_0
E8
0
IO_L37N_0
B8
0
IO_L37P_0
A8
0
IO_L39N_0
H9
0
IO_L39P_0
G9
0
IO_L43N_0
F9
0
IO_L43P_0
E9
0
IO_L45N_0
D9
0
IO_L45P_0/VREF_0
C9
0
IO_L46N_0
H10
0
IO_L46P_0
H11
0
IO_L48N_0
E10
0
IO_L48P_0
E11
0
IO_L49N_0
D10
0
IO_L49P_0
C10
0
IO_L50_0/No_Pair
G11
0
IO_L53_0/No_Pair
F11
0
IO_L54N_0
J12
0
IO_L54P_0
H12
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
30