DS083 Datasheet, PDF (103/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Clock Distribution Switching Characteristics
Table 38: Clock Distribution Switching Characteristics
Description
Global Clock Buffer I input to O output
Global Clock Buffer S input Setup/Hold
to I1 an I2 inputs
Symbol
T_GIO
T_GSI/T_GIS
Speed Grade
-7
-6
-5
0.05
0.057
0.064
Units
ns, max
0.49/–0.10 0.54/–0.12 0.60/–0.13 ns, max
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 34 in Module 2). The values listed below
are worst-case. Precise values are provided by the timing analyzer.
Table 39: CLB Switching Characteristics
Speed Grade
Description
Symbol
-7
-6
-5
Units
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
FXINA or FXINB inputs to Y output via MUXFX
FXINA input to FX output via MUXFX
FXINB input to FX output via MUXFX
SOPIN input to SOPOUT output via ORCY
Incremental delay routing through transparent latch to
XQ/YQ outputs
T_ILO
T_IF5
T_IF5X
T_IFXY
T_INAFX
T_INBFX
T_SOPSOP
T_IFNCTL
0.28
0.32
0.36
ns, max
0.59
0.65
0.73
ns, max
0.63
0.70
0.79
ns, max
0.29
0.32
0.36
ns, max
0.29
0.32
0.36
ns, max
0.29
0.32
0.36
ns, max
0.11
0.13
0.14
ns, max
0.23
0.24
0.27
ns, max
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times Before/After Clock CLK
T_CKO
T_CKLO
0.37
0.38
0.42
ns, max
0.54
0.57
0.64
ns, max
BX/BY inputs
DY inputs
DX inputs
CE input
SR/BY inputs (synchronous)
Clock CLK
T_DICK/T_CKDI
T_DYCK/T_CKDY
T_DXCK/T_CKDX
T_CECK/T_CKCE
T_{RCK /}T_CKR
0.21/–0.04
0.00/ 0.12
0.00/ 0.12
0.27/ 0.01
0.55/–0.01
0.24/–0.05
0.00/ 0.14
0.00/ 0.14
0.34/ 0.01
0.60/–0.01
0.27/–0.06
0.00/ 0.15
0.00/ 0.15
0.47/ 0.01
0.78/–0.01
ns, min
ns, min
ns, min
ns, min
ns, min
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
T_CH
0.37
0.40
0.45
ns, min
T_CL
0.37
0.40
0.45
ns, min
Minimum Pulse Width, SR/BY inputs (asynchronous)
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
T_RPW
T_RQ
0.37
0.40
0.45
ns, min
1.09
1.25
1.40
ns, max
Toggle Frequency (for export control)
F_TOG
1350
1200
1050
MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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