DS083 Datasheet, PDF (54/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
3-State Buffers
Introduction
Each Virtex-II Pro CLB contains two 3-state drivers
(TBUFs) that can drive on-chip buses. Each 3-state buffer
has its own 3-state control pin and its own input pin.
Each of the four slices have access to the two 3-state buff-
ers through the switch matrix, as shown in Figure 45.
TBUFs in neighboring CLBs can access slice outputs by
direct connects. The outputs of the 3-state buffers drive hor-
izontal routing resources used to implement 3-state buses.
TBUF
Switch
Matrix
TBUF
Slice
S1
Slice
S3
Slice
S2
Slice
S0
DS031_37_060700
Figure 45: Virtex-II Pro 3-State Buffers
The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predict-
able and less load dependant especially with larger devices.
Locations / Organization
Four horizontal routing resources per CLB are provided for
on-chip 3-state buses. Each 3-state buffer has access alter-
nately to two horizontal lines, which can be partitioned as
shown in Figure 46. The switch matrices corresponding to
SelectRAM+ memory and multiplier or I/O blocks are
skipped.
Number of 3-State Buffers
Table 18 shows the number of 3-state buffers available in
each Virtex-II Pro device. The number of 3-state buffers is
twice the number of CLB elements.
Table 18: Virtex-II Pro 3-State Buffers
Device
3-State Buffers Total Number
per Row
of 3-State Buffers
XC2VP2
44
704
XC2VP4
44
1,504
XC2VP7
68
2,464
XC2VP20
92
4,640
XC2VPX20
92
4,896
XC2VP30
92
6,848
XC2VP40
116
9,696
XC2VP50
140
11,808
XC2VP70
164
16,544
XC2VPX70
164
16,544
XC2VP100
188
22,048
3 - state lines
Switch
matrix
CLB-II
Programmable
connection
Switch
matrix
CLB-II
DS031_09_032700
Figure 46: 3-State Buffer Connection to Horizontal Lines
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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