DS083 Datasheet, PDF (179/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FF672 Flip-Chip Fine-Pitch BGA Package
As shown in Table 8, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FF672 flip-chip fine-pitch
BGA package. Pins in each of these devices are the same, except for differences shown in the "No Connects" column.
Following this table are the FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L03P_0/VREF_0
IO_L05_0/No_Pair
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0/VREF_0
IO_L37N_0
IO_L37P_0
IO_L38N_0
IO_L38P_0
IO_L39N_0
IO_L39P_0
IO_L43N_0
IO_L43P_0
IO_L44N_0
IO_L44P_0
IO_L45N_0
IO_L45P_0/VREF_0
IO_L67N_0
IO_L67P_0
IO_L68N_0
IO_L68P_0
IO_L69N_0
IO_L69P_0/VREF_0
Pin
Number
B24
A24
D21
C21
E20
D20
F19
E19
E18
D19
C19
B19
A19
G18
F18
D18
C18
G17
H16
F17
F16
E17
D17
G16
G15
E16
D16
F15
E15
D15
C15
H15
H14
XC2VP2
No Connects
XC2VP4
XC2VP7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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