DS083 Datasheet, PDF (81/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 14 shows internal (register-to-register) performance. Values are reported in MHz.
Table 14: Register-to-Register Performance
Description
Basic Functions:
16-bit Address Decoder
32-bit Address Decoder
64-bit Address Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
Register to LUT to Register
8-bit Adder
16-bit Adder
32-bit Adder
64-bit Adder
128-bit Adder
24-bit Counter
64-bit Counter
64-bit Accumulator
Multiplier 18x18 (with Block RAM inputs)
Multiplier 18x18 (with Register inputs)
Memory:
Block RAM
Single-Port 4096 x 4 bits
Distributed RAM
Single-Port 16 x 8-bit
Single-Port 32 x 8-bit
Single-Port 64 x 8-bit
Single-Port 128 x 8-bit
Dual-Port 16 x 8-bit
Dual-Port 32 x 8-bit
Dual-Port 64 x 8-bit
Device Used & Speed Grade
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
XC2VP20FF1152-6
Register-to-Register
Performance
547
392
310
710
609
472
400
1046
337
334
252
202
131
309
207
150
135
147
355
555
557
408
336
549
460
407
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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