DS083 Datasheet, PDF (134/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 4: Virtex-II Pro Pin Definitions (Continued)
Pin Name
Direction
Description
BREFCLKN,
BREFCLKP⁽²⁾
Input
Differential clock input that clocks the RocketIO X MGTs populating the same side of
the chip (top or bottom). Can also drive DCMs for RocketIO X MGT use.
VTRXPAD#
Input
Receive termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
VTTXPAD#
Input
Transmit termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
GNDA#
Input
Ground for the analog circuitry of the RocketIO multi-gigabit transceiver.
RXPPAD#
Input
Positive differential receive port of the RocketIO multi-gigabit transceiver.
RXNPAD#
Input
Negative differential receive port of the RocketIO multi-gigabit transceiver.
TXPPAD#
Output Positive differential transmit port of the RocketIO multi-gigabit transceiver.
TXNPAD#
Output
Negative differential transmit port of the RocketIO multi-gigabit transceiver.
Notes:
1. All dedicated pins (JTAG and configuration) are powered by V_CCAUX (independent of the bank V_CCO voltage).
2. Virtex-II Pro X devices XC2VPX20 and XC2VPX70 only. Each BREFCLK(N/P) differential clock input pair takes the place of one
regular Virtex-II Pro dual-function IO/GCLKx(S/P) pair on each side of the chip (top or bottom). For RocketIO BREFCLK, see section
BREFCLK Pin Definitions (RocketIO Only) immediately following.
BREFCLK Pin Definitions (RocketIO Only)
These dedicated clocks use the same clock inputs for all packages:
P GCLK4S
P GCLK6P
BREFCLK
BREFCLK
N GCLK5P
N GCLK7S
Top
Bottom
P GCLK2S
P GCLK0P
BREFCLK2
BREFCLK2
N GCLK3P
N GCLK1S
For detailed information about using BREFCLK/BREFCLK2, including routing considerations and pin numbers for all
package types, refer to Chapter 2, "Digital Design Considerations," in the RocketIO Transceiver User Guide.
DS083 (v4.7) November 5, 2007
Product Specification
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