DS083 Datasheet, PDF (116/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
DCM Timing Parameters
All devices are 100% functionally tested. Because of the dif-
ficulty in directly measuring many internal timing parame-
ters, those parameters are derived from benchmark timing
patterns. The following guidelines reflect worst-case values
across the recommended operating conditions. All output
jitter and phase specifications are determined through sta-
tistical measurement at the package pins.
Operating Frequency Ranges
e
Table 54: Operating Frequency Ranges
Speed Grade
Description
Symbol
Constraints -7
-6
-5 Units
Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270
CLKOUT_FREQ_1X_LF_MIN
24.00
24.00
24.00 MHz
CLK2X, CLK2X180^(5,6)
CLKOUT_FREQ_1X_LF_MAX
CLKOUT_FREQ_2X_LF_MIN
270.00
48.00
210.00
48.00
180.00 MHz
48.00 MHz
CLKOUT_FREQ_2X_LF_MAX
450.00 420.00 360.00 MHz
CLKDV
CLKOUT_FREQ_DV_LF_MIN
1.50
1.50
1.50 MHz
CLKOUT_FREQ_DV_LF_MAX
140.00 140.00 120.00 MHz
CLKFX, CLKFX180
CLKOUT_FREQ_FX_LF_MIN
24.00
24.00
24.00 MHz
CLKOUT_FREQ_FX_LF_MAX
240.00 240.00 210.00 MHz
Input Clocks (Low Frequency Mode)
CLKIN (using DLL outputs)^(1,3,4)
CLKIN_FREQ_DLL_LF_MIN
24.00
24.00
24.00 MHz
CLKIN (using CLKFX outputs)^(2,3,4)
CLKIN_FREQ_DLL_LF_MAX
CLKIN_FREQ_FX_LF_MIN
270.00
1.00
210.00
1.00
180.00 MHz
1.00 MHz
CLKIN_FREQ_FX_LF_MAX
240.00 240.00 210.00 MHz
PSCLK
PSCLK_FREQ_LF_MIN
0.01
0.01
0.01 MHz
PSCLK_FREQ_LF_MAX
450.00 420.00 360.00 MHz
Output Clocks (High Frequency Mode)
CLK0, CLK180⁽⁶⁾
CLKOUT_FREQ_1X_HF_MIN
48.00
48.00
48.00 MHz
CLKOUT_FREQ_1X_HF_MAX
450.00 420.00 360.00 MHz
CLKDV
CLKOUT_FREQ_DV_HF_MIN
3.00
3.00
3.00 MHz
CLKOUT_FREQ_DV_HF_MAX
280.00 280.00 240.00 MHz
CLKFX, CLKFX180
CLKOUT_FREQ_FX_HF_MIN
210.00 210.00 210.00 MHz
CLKOUT_FREQ_FX_HF_MAX
320.00 320.00 270.00 MHz
Input Clocks (High Frequency Mode)
CLKIN (using DLL outputs)^(1,3,4,6)
CLKIN_FREQ_DLL_HF_MIN
48.00
48.00
48.00 MHz
CLKIN (using CLKFX outputs)^(2,3,4)
CLKIN_FREQ_DLL_HF_MAX
CLKIN_FREQ_FX_HF_MIN
450.00
50.00
420.00
50.00
360.00 MHz
50.00 MHz
CLKIN_FREQ_FX_HF_MAX
320.00 320.00 270.00 MHz
PSCLK
PSCLK_FREQ_HF_MIN
0.01
0.01
0.01 MHz
PSCLK_FREQ_HF_MAX
450.00 420.00 360.00 MHz
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
3. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.
4. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used and CLKIN frequency > 400 MHz, CLKIN duty cycle must be within ±5%
(45/55 to 55/45).
5. CLK2X and CLK2X180 may not be used as the input to the CLKFB pin. See the Virtex-II Pro Platform FPGA User Guide for more
information.
6. For the XC2VP100 -6 device only, clock macros for corner DCMS (X0Y0, X5Y0, X0Y1, X5Y1) are required to operate at maximum
clock frequency. See XAPP685 for implementation examples.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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