DS083 Datasheet, PDF (226/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FF1152 Flip-Chip Fine-Pitch BGA Package
As shown in Table 10, XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Virtex-II Pro devices are available in the FF1152
flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the differences shown in the No
Connect column. Following this table are the FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 10: FF1152 — XC2VP20, XC2VP30, XC2VP40, and XC2VP50
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L03P_0/VREF_0
IO_L05_0/No_Pair
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0/VREF_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0
IO_L27N_0
IO_L27P_0/VREF_0
IO_L37N_0
IO_L37P_0
IO_L38N_0
IO_L38P_0
IO_L39N_0
IO_L39P_0
IO_L43N_0
Pin
Number
E29
E28
H26
G26
H25
G25
J25
K24
J24
F26
E26
D30
D29
K23
J23
F24
E24
D28
C28
H24
G24
G23
F23
E27
D27
K22
J22
H22
G22
D26
C26
K21
J21
F22
XC2VP20
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
No Connects
XC2VP30 XC2VP40
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
XC2VP50
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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