DS083 Datasheet, PDF (129/430 Pages) Xilinx, Inc – Summary of Features

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R 0 Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
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Pinout Information
DS083 (v4.7) November 5, 2007
Product Specification
This document provides Virtex™-II Pro Device/Package
Combinations, Maximum I/Os, and Virtex-II Pro Pin Defini-
tions, followed by pinout tables, for these packages:
• FG256/FGG256 Fine-Pitch BGA Package
• FG456/FGG456 Fine-Pitch BGA Package
• FG676/FGG676 Fine-Pitch BGA Package
• FF672 Flip-Chip Fine-Pitch BGA Package
• FF896 Flip-Chip Fine-Pitch BGA Package
• FF1152 Flip-Chip Fine-Pitch BGA Package
• FF1148 Flip-Chip Fine-Pitch BGA Package
• FF1517 Flip-Chip Fine-Pitch BGA Package
• FF1704 Flip-Chip Fine-Pitch BGA Package
• FF1696 Flip-Chip Fine-Pitch BGA Package
For device pinout diagrams and layout guidelines, refer to
the Virtex-II Pro Platform FPGA User Guide. ASCII package
pinout files are also available for download from the Xilinx
website (www.xilinx.com).
Virtex-II Pro Device/Package Combinations and Maximum I/Os⁽¹⁾
Wire-bond and flip-chip packages are available. Table 1 and
Table 2 show the maximum number of user I/Os possible in
wire-bond and flip-chip packages, respectively.
• FG denotes wire-bond fine-pitch BGA
(1.00 mm pitch).
.
Table 1: Wire-Bond Packages Information
Package ⁽¹⁾
FG256/
FGG256
FG456/
FGG456
FG676/
FGG676
Pitch (mm)
1.00
1.00
1.00
• FGG denotes Pb-free wire-bond fine-pitch BGA
(1.00 mm pitch).
• FF denotes flip-chip fine-pitch BGA
(1.00 mm pitch)
Size (mm)
17 x 17
23 x 23
26 x 26
Maximum I/Os
140
248
412
Notes:
1. Wire-bond packages include FGGnnn Pb-free versions. See
Virtex-II Pro Ordering Examples (Module 1).
Table 2: Flip-Chip Packages Information
Package
FF672
FF896
FF1152
FF1148
FF1517
FF1704
FF1696
Pitch (mm)
1.00
1.00
1.00
1.00
1.00
1.00
1.00
Size (mm)
27 x 27
31 x 31
35 x 35
35 x 35
40 x 40 42.5 x 42.5 42.5 x 42.5
Maximum I/Os
396
556
644
812
964
1040
1200
Table 3 shows the number of available I/Os, the number of RocketIO™ (or RocketIO X) multi-gigabit transceiver (MGT) pins,
and the number of differential I/O pairs for each Virtex-II Pro device/package combination. The number of I/Os per package
includes all user I/Os except the fifteen control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO,
TMS, HSWAP_EN, DXN, DXP, and RSVD), the nine (per transceiver) RocketIO MGT pins (TXP, TXN, RXP, RXN,
AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA), and for Virtex-II Pro X devices only, the two BREFCLKN/
BREFCLKP differential clock input pairs (four pins). The Virtex-II Pro X devices are highlighted in bold type.
1. Unless otherwise noted, "Virtex-II Pro" refers to members of the Virtex-II Pro and/or Virtex-II Pro X families.
© 2002–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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