DS083 Datasheet, PDF (92/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVCMOS 2.5V levels. For other standards, adjust the delays with the
values shown in IOB Input Switching Characteristics Standard Adjustments.
Table 32: IOB Input Switching Characteristics
Description
Propagation Delays
Pad to I output, no delay
Pad to I output, with delay
Symbol
T_IOPI
T_IOPID
Propagation Delays
Pad to output IQ via transparent latch,
no delay
Pad to output IQ via transparent latch,
with delay
T_IOPLI
T_IOPLID
Clock CLK to output IQ
T_IOCKIQ
Device
Speed Grade
-7
-6
-5
Units
All
0.84
XC2VP2
1.84
XC2VP4
1.84
XC2VP7
1.84
XC2VP20
2.14
XC2VPX20
2.14
XC2VP30
2.14
XC2VP40
2.54
XC2VP50
2.54
XC2VP70
2.54
XC2VPX70
2.54
XC2VP100
N/A
0.87
0.91
ns, max
1.94
2.06
ns, max
1.94
2.06
ns, max
1.94
2.06
ns, max
2.23
2.37
ns, max
2.23
2.37
ns, max
2.26
2.46
ns, max
2.67
2.81
ns, max
2.68
2.87
ns, max
2.72
2.91
ns, max
2.72
2.91
ns, max
4.71
4.80
ns, max
All
0.86
XC2VP2
2.30
XC2VP4
2.57
XC2VP7
2.50
XC2VP20
2.65
XC2VPX20
2.65
XC2VP30
2.69
XC2VP40
3.30
XC2VP50
3.86
XC2VP70
4.00
XC2VPX70
4.00
XC2VP100
N/A
All
0.60
0.89
0.93
ns, max
2.62
2.97
ns, max
2.89
3.23
ns, max
2.84
3.17
ns, max
3.04
3.42
ns, max
3.04
3.42
ns, max
3.12
3.51
ns, max
3.63
4.03
ns, max
4.10
4.45
ns, max
4.25
4.57
ns, max
4.25
4.57
ns, max
6.50
7.06
ns, max
0.60
0.67
ns, max
DS083 (v4.7) November 5, 2007
Product Specification
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