DS083 Datasheet, PDF (84/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 19: Processor Block JTAG Switching Characteristics
Description
Setup and Hold Relative to Clock (JTAGC405TCK)
JTAG control inputs
JTAG reset input
Clock to Out
JTAG control outputs
Symbol
T_PCCK_JTAG/
T_PCKC_JTAG
T_PCCK_JTAGRST/
T_PCKC_JTAGRST
T_PCKCO_JTAG
Speed Grade
-7
-6
-5
0.80/ 0.70 0.80/ 0.70 0.88/ 0.77
0.80/ 0.70 0.80/ 0.70 0.88/ 0.77
1.34
1.54
1.69
Units
ns, min
ns, min
ns, max
Table 20: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics
Speed Grade
Description
Symbol
-7
-6
-5
Setup and Hold Relative to Clock
(BRAMDSOCMCLK)
Data-Side On-Chip Memory data bus inputs
Clock to Out
T_PDCK_DSOCM/
T_PCKD_DSOCM
0.73/ 0.83
0.84/ 0.95
0.92/ 1.05
Data-Side On-Chip Memory control outputs
T_PCKCO_DSOCM
1.58
1.82
1.99
Data-Side On-Chip Memory address bus outputs
T_PCKAO_DSOCM
1.46
1.68
1.84
Data-Side On-Chip Memory data bus outputs
T_PCKDO_DSOCM
0.90
1.03
1.13
Units
ns, min
ns, max
ns, max
ns, max
Table 21: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics
Speed Grade
Description
Symbol
-7
-6
-5
Setup and Hold Relative to Clock (BRAMISOCMCLK)
Instruction-Side On-Chip Memory data bus inputs
Clock to Out
T_PDCK_ISOCM/
T_PCKD_ISOCM
0.81/ 0.68 0.93/ 0.78 1.02/ 0.86
Instruction-Side On-Chip Memory control outputs
T_PCKCO_ISOCM
1.33
Instruction-Side On-Chip Memory address bus outputs T_PCKAO_ISOCM
1.52
Instruction-Side On-Chip Memory data bus outputs
T_PCKDO_ISOCM
1.35
1.53
1.75
1.55
1.68
1.92
1.70
Units
ns, min
ns, max
ns, max
ns, max
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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