DS083 Datasheet, PDF (68/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Master SelectMAP Mode
This mode is a master version of the SelectMAP mode. The
device is configured byte-wide on a CCLK supplied by the
Virtex-II Pro FPGA device. Timing is similar to the Slave
SerialMAP mode except that CCLK is supplied by the
Virtex-II Pro FPGA.
Boundary-Scan (JTAG, IEEE 1532) Mode
In Boundary-Scan mode, dedicated pins are used for con-
figuring the Virtex-II Pro device. The configuration is done
entirely through the IEEE 1149.1 Test Access Port (TAP).
Virtex-II Pro device configuration using Boundary-Scan is
compatible with with IEEE 1149.1-1993 standard and the
new IEEE 1532 standard for In-System Configurable (ISC)
devices. The IEEE 1532 standard is backward compliant
with the IEEE 1149.1-1993 TAP and state machine. The
IEEE Standard 1532 for In-System Configurable (ISC)
devices is intended to be programmed, reprogrammed, or
tested on the board via a physical and logical protocol. Con-
figuration through the Boundary-Scan port is always avail-
able, independent of the mode selection. Selecting the
Boundary-Scan mode simply turns off the other modes.
Table 32: Virtex-II Pro Configuration Mode Pin Settings
Configuration Mode⁽¹⁾
M2
M1
M0
Master Serial
0
0
0
CCLK Direction
Out
Data Width
1
Serial D_OUT ⁽²⁾
Yes
Slave Serial
1
1
1
In
1
Yes
Master SelectMAP
0
1
1
Out
8
No
Slave SelectMAP
1
1
0
In
8
No
Boundary-Scan
1
0
1
N/A
1
No
Notes:
1. The HSWAP_EN pin controls the pull-ups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin
controls whether or not the pull-ups are used.
2. Daisy chaining is possible only in modes where Serial D_OUT is used. For example, in SelectMAP modes, the first device does NOT
support daisy chaining of downstream devices.
Table 33 lists the default total number of bits required to
configure each device.
Table 33: Virtex-II Pro Default Bitstream Lengths
Device
Number of Configuration
Bits
XC2VP2
1,305,376
XC2VP4
3,006,496
XC2VP7
4,485,408
XC2VP20
8,214,560
XC2VPX20
8,214,560
XC2VP30
11,589,920
XC2VP40
15,868,192
XC2VP50
19,021,344
XC2VP70
26,098,976
XC2VPX70
26,098,976
XC2VP100
34,292,768
Configuration Sequence
The configuration of Virtex-II Pro devices is a three-phase
process. First, the configuration memory is cleared. Next,
configuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user. The INIT_B pin can be held Low
using an open-drain driver. An open-drain is required since
INIT_B is a bidirectional open-drain pin that is held Low by a
Virtex-II Pro FPGA device while the configuration memory
is being cleared. Extending the time that the pin is Low
causes the configuration sequencer to wait. Thus, configu-
ration is delayed by preventing entry into the phase where
data is loaded.
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High, and the completion
of the entire process is signaled by the DONE pin going
High. The Global Set/Reset (GSR) signal is pulsed after the
last frame of configuration data is written but before the
start-up sequence. The GSR signal resets all flip-flops on
the device.
The default start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary. One CCLK cycle later, the Global Write Enable (GWE)
signal is released. This permits the internal storage ele-
ments to begin changing state in response to the logic and
the user clock.
The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
57