DS083 Datasheet, PDF (89/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 27: RocketIO Transmitter Switching Characteristics
Description
Symbol
Conditions
Min
Typ
Max Units
Serial data rate, full-speed clock
Serial data rate, half-speed clock⁽³⁾
(2X oversampling)
F_GTX
Flipchip packages
Wirebond packages
Flipchip packages
Wirebond packages
1.0
1.0
0.600
0.600
3.125 ⁽¹⁾
2.5⁽¹⁾
1.0
1.0
Gb/s
Gb/s
Gb/s
Gb/s
2.126 Gb/s – 3.125 Gb/s
0.17
UI⁽²⁾
Serial data output deterministic jitter
1.0626 Gb/s – 2.125 Gb/s
T_DJ
1.0 Gb/s – 1.0625 Gb/s
600 Mb/s – 999 Mb/s
0.08
UI
0.05
UI
0.08⁽⁴⁾
UI
2.126 Gb/s – 3.125 Gb/s
0.18
UI
Serial data output random jitter
1.0626 Gb/s – 2.125 Gb/s
T_RJ
1.0 Gb/s – 1.0625 Gb/s
0.19
UI
0.18
UI
600 Mb/s – 999 Mb/s
0.18⁽⁴⁾
UI
TX rise time
TX fall time
Transmit latency⁽⁵⁾
T_RTX
T_FTX
T_TXLAT
20% – 80%
Including CRC
Excluding CRC
120
ps
120
ps
14
17
TXUSR
CLK
8
11
cycles
TXUSRCLK duty cycle
T_TXDC
45
50
55
%
TXUSRCLK2 duty cycle
T_TX2DC
45
50
55
%
Notes:
1. Serial data rate in the -5 speed grade is limited to 2.0 Gb/s in both wirebond and flipchip packages.
2. UI = Unit Interval
3. For serial rates under 1 Gb/s, the 3X (or greater) oversampling techniques described in XAPP572 are required to meet the transmit jitter and
receive jitter tolerance specifications defined in this data sheet.
4. The oversampling techniques described in XAPP572 are required to meet these specifications for serial rates less than 1 Gb/s.
5. Transmit latency delay TXDATA to TXP/TXN. Refer to RocketIO Transceiver User Guide for more information on calculating latency.
1 2 ^{. . . . .} 20 21 22
TXP/TXN
TXDATA[16:0]
DATA ORIGINATES
.....
T_TXLAT
320 321 322 ^{. . . . .} 340 341 342 ^{. . . .}
DATA ARRIVES
0
1
TXUSRCLK2
16
17
Figure 5: RocketIO Transmit Latency (Maximum, Including CRC)
DS083-3_03_082301
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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