DS083 Datasheet, PDF (123/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Virtex-II Pro Receiver Data-Valid Window (R_X)
R_X is the required minimum aggregate valid data period for
a source-synchronous data bus at the pins of the device
and is calculated as follows:
R_X = [TSAMP⁽¹⁾ + TCKSKEW⁽²⁾ + TPKGSKEW⁽³⁾ ]
Notes:
1. This parameter indicates the total sampling error of
Virtex-II Pro DDR input registers across voltage, temperature,
and process. The characterization methodology uses the DCM
to capture the DDR input registers’ edges of operation. These
measurements include:
- CLK0 and CLK180 DCM jitter in a quiet system
- Worst-case duty-cycle distortion
- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree
skew.
2. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
3. These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
Revision History
This section records the change history for this module of the data sheet.
Date
01/31/02
06/17/02
09/03/02
09/27/02
11/20/02
11/25/02
Version
1.0
2.0
2.1
2.2
2.3
2.4
Revision
Initial Xilinx release.
• Added new Virtex-II Pro family members.
• Added timing parameters from speedsfile v1.62.
• Added Table 43, Pipelined Multiplier Switching Characteristics.
• Added 3.3V-vs-2.5V table entries for some parameters.
• Added Source-Synchronous Switching Characteristics section.
• Added absolute max ratings for 3.3V-vs-2.5V parameters in Table 1.
• Added recommended operating conditions for V_IN and RocketIO footnote to Table 2.
• Updated SSTL2 values in Table 6. Added SSTL18 values: Table 6, Table 36, Table 32.
[Table 32 removed in v2.8.]
• Added Table 10, which contains LVPECL DC specifications.
Added section General Power Supply Requirements.
Updated parametric information in:
• Table 1: Increase Absolute Max Rating for V_CCO, V_REF, V_IN, and V_TS from 3.6V to
3.75V. Delete cautionary footnotes related to voltage overshoot/undershoot.
• Table 2: Delete V_CCO specifications for 2.5V and below operation. Delete footnote
referencing special information for 3.3V operation. Add footnote for PCI/PCI-X.
• Table 3: Add I_BATT. Delete I_L specifications for 2.5V and below operation.
• Table 4: Add Typical Quiescent Supply Currents for XC2VP4 and XC2VP7 only
• Table 6: Correct I_OL and I_OH for SSTL2 I. Add rows for LVTTL, LVCMOS33, and PCI-X.
Correct max V_IH from V_CCO to 3.6V.
• Table 7: Correct Min/Max V_OD, V_OCM, and V_ICM
• Table 10: Reformat LVPECL DC Specifications to match Virtex-II data sheet format
• Table 12: Correct parameter name from Differential Output Voltage to Single-Ended
Output Voltage Swing.
• Table 16: Add CPMC405CLOCK max frequencies
• Table 27: Add footnote regarding serial data rate limitation in -5 part.
• Table 36: Add rows for LVTTL, LVCMOS33, and PCI-X.
• Table 32: Add LVTTL, LVCMOS33, and PCI-X. Correct all capacitive load values
(except PCI/PCI-X) to 0 pF. [Table 32 removed in v2.8.]
• Table 48: Correct CCLK max frequencies
Table 1: Correct lower limit of voltage range of V_IN and V_TS from –0.3V to –0.5V for 3.3V.
DS083 (v4.7) November 5, 2007
Product Specification
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