DS083 Datasheet, PDF (60/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
8 clock pads
Virtex-II Pro
Device
8 clock pads
DS083-2_42_052902
Figure 55: Virtex-II Pro Clock Pads
Each global clock multiplexer buffer can be driven either by
the clock pad to distribute a clock directly to the device, or
by the Digital Clock Manager (DCM), discussed in Digital
Clock Manager (DCM), page 51. Each global clock multi-
plexer buffer can also be driven by local interconnects. The
DCM has clock output(s) that can be connected to global
clock multiplexer buffer inputs, as shown in Figure 56.
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM+ blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II Pro device. Designers should consider the clock
distribution detail of the device prior to pin-locking and floor-
planning. (See the Virtex-II Pro Platform FPGA User
Guide.)
Clock
Pad
Clock
Pad
CLKIN
DCM
CLKOUT
Local
Interconnect
Clock Multiplexer
I
Clock
Buffer
O
Clock Distribution
DS083-2_43_122001
Figure 56: Virtex-II Pro Clock Multiplexer Buffer Configuration
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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