DS083 Datasheet, PDF (121/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 62: Package Skew
Description
Symbol
Device/Package
Value
Units
Package Skew⁽¹⁾
T_PKGSKEW
XC2VP2FF672
XC2VP4FF672
104
ps
102
ps
XC2VP7FF672
92
ps
XC2VP7FF896
101
ps
XC2VP20FF896
93
ps
XC2VPX20FF896
93
ps
XC2VP20FF1152
106
ps
XC2VP30FF896
86
ps
XC2VP30FF1152
112
ps
XC2VP40FF1152
92
ps
XC2VP40FF1148
100
ps
XC2VP50FF1152
88
ps
XC2VP50FF1148
101
ps
XC2VP50FF1517
97
ps
XC2VP70FF1517
95
ps
XC2VP70FF1704
101
ps
XC2VPX70FF1704
101
ps
XC2VP100FF1704
86
ps
XC2VP100FF1696
100
ps
Notes:
1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad
to Ball (7.1ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the
package.
Table 63: Sample Window
Speed Grade
Description
Symbol
Device
–7
–6
–5
Units
Sampling Error at Receiver Pins⁽¹⁾
T_SAMP
All
0.50
0.50
0.50
ns
Notes:
1. This parameter indicates the total sampling error of Virtex-II Pro DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation.
2. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case duty-cycle distortion, T_{DCD_CLK180}
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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