DS083 Datasheet, PDF (119/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Miscellaneous Timing Parameters
Table 58: Miscellaneous Timing Parameters
Speed Grade
Description
Time Required to Achieve LOCK
Using DLL outputs⁽¹⁾
Symbol
LOCK_DLL:
Constraints
F_CLKIN
-7
-6
-5 Units
LOCK_DLL_60
> 60MHz
20.00
20.00
20.00 us
LOCK_DLL_50_60
50 - 60 MHz
25.00
25.00
25.00 us
LOCK_DLL_40_50
LOCK_DLL_30_40
40 - 50 MHz
30 - 40 MHz
50.00
90.00
50.00
90.00
50.00 us
90.00 us
LOCK_DLL_24_30
24 - 30 MHz
120.00 120.00 120.00 us
Using CLKFX outputs
LOCK_FX_MIN
10.00
10.00
10.00 ms
LOCK_FX_MAX
10.00
10.00
10.00 ms
Additional lock time with fine phase
shifting
LOCK_DLL_FINE_SHIFT
50.00
50.00
50.00 us
Fine Phase Shifting
Absolute shifting range
FINE_SHIFT_RANGE
10.00
10.00
10.00 ns
Delay Lines
Tap delay resolution
DCM_TAP_MIN
30.00
30.00
30.00 ps
DCM_TAP_MAX
50.00
50.00
50.00 ps
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
Frequency Synthesis
Table 59: Frequency Synthesis
Attribute
Min
Max
CLKFX_MULTIPLY
CLKFX_DIVIDE
2
32
1
32
Parameter Cross-Reference
Table 60: Parameter Cross-Reference
Libraries Guide
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
Data Sheet
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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