DS083 Datasheet, PDF (288/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 — XC2VP40 and XC2VP50
Bank
Pin Description
Pin Number
N/A
GND
AP5
N/A
GND
AK5
N/A
GND
AF5
N/A
GND
AB5
N/A
GND
W5
N/A
GND
T5
N/A
GND
N5
N/A
GND
J5
N/A
GND
E5
N/A
GND
A5
N/A
GND
AM3
N/A
GND
C3
N/A
GND
AN2
N/A
GND
B2
N/A
GND
AK1
N/A
GND
AF1
N/A
GND
AB1
N/A
GND
W1
N/A
GND
V1
N/A
GND
T1
N/A
GND
N1
N/A
GND
J1
N/A
GND
E1
Notes:
1. See Table 4 for an explanation of the signals available on this pin.
No Connects
XC2VP40
XC2VP50
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
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