DS083 Datasheet, PDF (108/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Configuration Timing
Configuration Memory Clearing Parameters
Power-up timing of configuration signals is shown in Figure 7; corresponding timing characteristics are listed in Table 46.
V_CC
PROG_B
INIT_B
CCLK
(Output
or Input)
M0, M1, M2*
(Required)
1 T_POR
2 ^TPL
3
T_ICCK
*Can be either 0 or 1, but must not toggle during and after configuration.
ds083-3_07_012004
Figure 7: Configuration Power-Up Timing
Table 46: Power-Up Timing Characteristics
Description
Figure
References
Symbol
Value
Units
Power-on reset
Program latency
CCLK (output) delay
1
T_POR
T_PL + 2
ms, max
2
T_PL
4
μs per frame, max
0.25
μs, min
3
T_ICCK
4.00
μs, max
Program pulse width
T_PROGRAM
300
ns, min
Notes:
1. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied
directly to ground or V_CCAUX. The mode pins should not be toggled during and after configuration.
DS083 (v4.7) November 5, 2007
Product Specification
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