DS083 Datasheet, PDF (45/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Figure 30 provides examples illustrating the use of the
LVDS_25_DCI and LVDSEXT_25_DCI I/O standards. For a
complete list, see the Virtex-II Pro Platform FPGA User
Guide.
LVDS_25_DCI and LVDSEXT_25_DCI Receiver
Conventional
Z0
2R
The on-chip input differential termination in Virtex-II Pro
provides major advantages over the external resistor or the
DCI termination solution:
• Eliminates the stub at the receiver completely and
therefore greatly improve signal integrity
• Consumes less power than DCI termination
• Supports LDT (not supported by DCI termination)
• Frees up VRP/VRN pins
Figure 31 provides examples illustrating the use of the
LVDS_25_DT, LVDSEXT_25_DT, LDT_25_DT, and
ULVDS_25_DT I/O standards. For further details, refer to
Solution Record 17244. Also see the Virtex-II Pro Platform
FPGA User Guide for more design information.
Z0
Virtex-II Pro
LVDS
LVDS_25_DT, LVDSEXT_25_DT,
LDT_25_DT, and ULVDS_25_DT Receiver
Conventional
Transmit
DCI Receive
V_CCO
2R
Z0
2R
V_CCO
2R
Z0
2R
Virtex-II Pro
LVDS DCI
Conventional
Z0
2R
Z0
Virtex-II Pro
LVDS
Reference
Resistor
VRN = VRP = R = Z0
Recommended
50 Ω
Z0
NOTE: Only LVDS25_DCI is supported (VCCO = 2.5V only)
DS083-2_65c_022103
Figure 30: LVDS DCI Usage Examples
On-Chip Differential Termination
Virtex-II Pro provides a true 100Ω differential termination
(DT) across the input differential receiver terminals. The
LVDS_25_DT, LVDSEXT_25_DT, LDT_25_DT, and
ULVDS_25_DT standards support on-chip differential termi-
nation.
Conventional
Transmit,
On-Chip
Differential
Termination
Receive
Z0
100Ω
Z0
Virtex-II Pro
LVDS On-Chip
Differential
Termination
Recommended
Z0
50 Ω
NOTE: Only 2.5V LVDS standards are supported (VCCO = 2.5V only)
DS083-2_65e_052703
Figure 31: LVDS Differential Termination Usage
Examples
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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