DS083 Datasheet, PDF (87/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 25: RocketIO Receiver Switching Characteristics
Description
Symbol
Conditions
Min
Typ
Max
2.126 Gb/s – 3.125 Gb/s
0.65
Units
UI ⁽¹⁾
Receive total jitter tolerance
T_JTOL
1.0626 Gb/s – 2.125 Gb/s
1.0 Gb/s – 1.0625 Gb/s
600 Mb/s – 999 Mb/s
0.65
UI
0.68
UI
0.68⁽²⁾
UI
2.126 Gb/s – 3.125 Gb/s
0.41
UI
Receive deterministic jitter tolerance
T_DJTOL
1.0626 Gb/s – 2.125 Gb/s
1.0 Gb/s – 1.0625 Gb/s
0.43
UI
0.47
UI
600 Mb/s – 999 Mb/s
0.47⁽²⁾
Receive latency⁽³⁾
T_RXLAT
25
42⁽⁴⁾ RXUSRCLK cycles
RXUSRCLK duty cycle
T_RXDC
45
50
55
%
RXUSRCLK2 duty cycle
T_RX2DC
45
50
55
%
Notes:
1. UI = Unit Interval
2. The oversampling techniques described in XAPP572 are required to meet these specifications for serial rates less than 1 Gb/s.
3. Receive latency delay RXP/RXN to RXDATA. Refer to RocketIO Transceiver User Guide for more information on calculating latency.
4. This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled. If these functions are both
disabled, the maximum will be near the typical values.
DATA ORIGINATES
1 2 ^.....
RXP/RXN
20 21 22
.....
820 821 822 ^{. . . . .}
840 841 842
....
RXDATA[16:0]
T_RXLAT
DATA ARRIVES
0
RXUSRCLK2
1
41
Figure 4: RocketIO Receive Latency (Maximum)
42
DS083-3_02_082301
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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