DS083 Datasheet, PDF (35/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Functional Description: FPGA
Input/Output Blocks (IOBs)
Virtex-II Pro I/O blocks (IOBs) are provided in groups of two
or four on the perimeter of each device. Each IOB can be
used as input and/or output for single-ended I/Os. Two IOBs
can be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
Figure 18.
IOB blocks are designed for high-performance I/O, support-
ing 22 single-ended standards, as well as differential sig-
naling with LVDS, LDT, bus LVDS, and LVPECL.
Switch
Matrix
IOB
PAD4
IOB
PAD3
IOB
PAD2
IOB
PAD1
Differential Pair
Differential Pair
DS083-2_30_010202
Figure 18: Virtex-II Pro Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II Pro IOB blocks feature SelectIO-Ultra inputs and
outputs that support a wide variety of I/O signaling stan-
dards. In addition to the internal supply voltage
(V_CCINT = 1.5V), output driver supply voltage (V_CCO) is
dependent on the I/O standard (see Table 8 and Table 9).
An auxiliary supply voltage (V_CCAUX = 2.5V) is required,
regardless of the I/O standard used. For exact supply volt-
age absolute maximum ratings, see Virtex-II Pro and
Virtex-II Pro X Platform FPGAs: DC and Switching Charac-
teristics.
All of the user IOBs have fixed-clamp diodes to V_CCO and to
ground. The IOBs are not compatible or compliant with 5V
I/O standards (not 5V-tolerant).
Table 10 lists supported I/O standards with Digitally Con-
trolled Impedance. See Digitally Controlled Impedance
(DCI), page 31.
Table 8: Supported Single-Ended I/O Standards
IOSTANDARD
Attribute
LVTTL⁽¹⁾
LVCMOS33⁽¹⁾
Output
V_CCO
3.3
3.3
Input
V_CCO
3.3
3.3
Input
V_REF
N/R
N/R
Board
Termination
Voltage (V_TT)
N/R
N/R
LVCMOS25
2.5
2.5
N/R
N/R
LVCMOS18
1.8
1.8
N/R
N/R
LVCMOS15
1.5
1.5
N/R
N/R
PCI33_3
Note (2) Note (2) N/R
N/R
PCI66_3
Note (2) Note (2) N/R
N/R
PCIX
Note (2) Note (2) N/R
N/R
GTL
Note (3) Note (3) 0.8
1.2
GTLP
Note (3) Note (3) 1.0
1.5
HSTL_I
1.5
N/R
0.75
0.75
HSTL_II
1.5
N/R
0.75
0.75
HSTL_III
1.5
N/R
0.9
1.5
HSTL_IV
1.5
N/R
0.9
1.5
HSTL_I_18
1.8
N/R
0.9
0.9
HSTL_II_18
1.8
N/R
0.9
0.9
HSTL_III _18
1.8
N/R
1.1
1.8
HSTL_IV_18
1.8
N/R
1.1
1.8
SSTL2_I
2.5
N/R
1.25
1.25
SSTL2_II
2.5
N/R
1.25
1.25
SSTL18_I ⁽⁴⁾
1.8
N/R
0.9
0.9
SSTL18_II
1.8
N/R
0.9
0.9
Notes:
1. Refer to XAPP659 for more details on interfacing to these 3.3V
standards.
2. For PCI and PCI-X standards, refer to XAPP653.
3. V_CCO of GTL or GTLP should not be lower than the termination
voltage or the voltage seen at the I/O pad. Example: If the pin High
level is 1.5V, connect V_CCO to 1.5V.
4. SSTL18_I is not a JEDEC-supported standard.
5. N/R = no requirement.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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