DS083 Datasheet, PDF (429/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Revision History
This section records the change history for this module of the data sheet.
Date
01/31/02
08/14/02
08/27/02
09/27/02
11/20/02
12/03/02
01/20/03
05/19/03
06/19/03
08/25/03
12/10/03
02/19/04
03/09/04
06/30/04
Version
1.0
2.0
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.3
2.5.5
3.0
3.1
3.1.1
4.0
Revision
Initial Xilinx release.
Added package and pinout information for new devices.
• Updated SelectIO-Ultra information in Table 4. (Table deleted in v2.3.)
• Corrected direction for RXNPAD and TXPPAD in Table 4 (formerly Table 5).
Corrected Table 2 and Table 3 entries for XC2VP30, FF1152 package, maximum I/Os from
692 to 644.
Added Number of Differential Pairs data to Table 3. Removed former Table 4.
Corrections in Table 4:
• Reclassified GCLKx (S/P) pins as Input/Output, since these pins can be used as
normal I/Os if not used as clocks.
• Added cautionary note to PWRDWN_B pin, indicating that this function is not
supported.
Added and removed package/pinout information for existing devices:
• In Table 1, added FG676 package information.
• In Table 3, added FG676 package option for XC2VP20, XC2VP30, and XC2VP40.
• In Table 12, removed FF1517 package option for XC2VP40.
• Added FG676 package pinouts (Table 7) for XC2VP20, XC2VP30, and XC2VP40.
• Added package diagram (Figure 3) for FG676 package.
• Added section BREFCLK Pin Definitions, page 5.
• Added clarification to Table 4 and all device pinout tables regarding the dual-use
nature of pins D0/DIN and BUSY/DOUT during configuration.
• Added notation of "open-drain" to TDO pin in Table 4.
• The final GND pin in each of six pinout tables was inadvertently deleted in v2.5.1. This
revision restores the deleted GND pins as follows:
- Pin A1, Table 6, page 16 (FG456)
- Pin AF26, Table 7, page 30 (FG676)
- Pin AN34, Table 10, page 98 (FF1152)
- Pin E1, Table 11, page 130 (FF1148)
- Pin C38, Table 12, page 162 (FF1517)
- Pin E1, Table 14, page 253 (FF1696)
• Table 4: Deleted Note 2, obsolete. There is only one GNDA pin per MGT.
• Table 4: Deleted pins ALT_VRP and ALT_VRN. Not used in Virtex-II Pro FPGAs.
• XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
-5 and -6, are released to Production status.
• Table 4, signal descriptions column:
- For signals TDI, TMS, and TCK, added: Pins are 3.3V-compatible.
- For signals M2, M1, M0, added: Tie to 3.3V only with 100Ω series resistor.
No toggling during or after configuration.
- For signal TDO, added: No internal pull-up. External pull-up to 3.3V OK with
resistor greater than 200Ω.
• Recompiled for backward compatibility with Acrobat 4 and above. No content
changes.
Merged in DS110-4 (Module 4 of Virtex-II Pro X data sheet). Added data on available
Pb-free packages and updated package diagrams for affected devices.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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