DS083 Datasheet, PDF (76/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current
during power-on to insure proper device initialization. The
actual current consumed depends on the power-on ramp
rate of the power supply.
The V_CCINT power supply must ramp on, monotonically, no
faster than 200 μs and no slower than 50 ms. Ramp-on is
defined as: 0 V_DC to minimum supply voltages (see
Table 2).
V_CCAUX and V_CCO can power on at any ramp rate. Power
supplies can be turned on in any sequence.
Table 5 shows the minimum current required by Virtex-II Pro
devices for proper power-on and configuration.
If the current minimums shown in Table 5 are met, the
device powers on properly after all three supplies have
passed through their power-on reset threshold voltages.
Once initialized and configured, use the power calculator to
estimate current drain on these supplies.
For more information on V_CCAUX, V_CCO, and configuration
mode, refer to Chapter 3 in the Virtex-II Pro Platform FPGA
User Guide.
Table 5: Power-On Current for Virtex-II Pro Devices
Device
Symbol XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Units
I_CCINTMIN 500
500
500
600
600
800
1050 1250 1700
1700
2200 mA
I_CCAUXMIN 250
250
250
250
250
250
250
250
250
250
250
mA
I_CCOMIN
100
100
100
100
100
100
100
100
100
100
100
mA
Notes:
1. Power-on current parameter values are specified for Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.5.
2. I_CCOMIN values listed here apply to the entire device (all banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential.
Consult Xilinx Application Note XAPP623 for detailed infor-
mation on power distribution system design.
V_CCAUX powers critical resources in the FPGA. Therefore,
this supply voltage is especially susceptible to power supply
noise. V_CCAUX can share a power plane with V_CCO, but only
if V_CCO does not have excessive noise. Staying within
simultaneously switching output (SSO) limits is essential for
keeping power supply noise to a minimum. Refer to
XAPP689, “Managing Ground Bounce in Large FPGAs,” to
determine the number of simultaneously switching outputs
allowed per bank at the package level.
Changes in V_CCAUX voltage beyond 200 mV peak-to-peak
should take place at a rate no faster than 10 mV per milli-
second.
Recommended practices that can help reduce jitter and
period distortion are described in Xilinx Answer Record
13756.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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