DS083 Datasheet, PDF (86/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 24: RocketIO X Receiver Switching Characteristics⁽¹⁾
Description
Receive total jitter tolerance
using default equalization and PRBS-15
pattern
Symbol
T_JTOL
Conditions
2.488 Gb/s
3.125 Gb/s
4.25 Gb/s
6.25 Gb/s
Min
Typ
Max
0.80
0.65
0.80
0.65
0.80
0.65
0.80
0.65
Units
UI ⁽²⁾
UI
UI
UI
2.488 Gb/s
0.30
UI
3.125 Gb/s
0.30
UI
Receive random jitter tolerance
T_RJTOL
4.25 Gb/s
0.30
UI
6.25 Gb/s
0.30
UI
2.488 Gb/s
0.30
0.15
UI
Receive sinusoidal jitter tolerance
measured at 70 MHz
T_SJTOL
3.125 Gb/s
4.25 Gb/s
0.30
0.15
UI
0.30
0.15
UI
6.25 Gb/s
0.30
0.15
UI
2.488 Gb/s
0.55
0.45
UI
Receive deterministic jitter tolerance
T_DJTOL
3.125 Gb/s
4.25 Gb/s
0.55
0.45
UI
0.55
0.45
UI
6.25 Gb/s
0.50
0.45
UI
Receive latency⁽³⁾
T_RXLAT
25
34⁽⁴⁾ RXUSRCLK cycles
RXUSRCLK duty cycle
T_RXDC
45
50
55
%
RXUSRCLK2 duty cycle
T_RX2DC
45
50
55
%
Differential receive input sensitivity
V_EYE
120
250
mV
Notes:
1. The XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
2. UI = Unit Interval
3. Receive latency delay RXP/RXN to RXDATA. Refer to RocketIO X Transceiver User Guide for more information on calculating latency.
4. This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled. If these functions are both
disabled, the maximum will be near the typical values.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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