DS083 Datasheet, PDF (112/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Virtex-II Pro Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
With DCM
Table 50: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
With DCM
Speed Grade
Description
Symbol
Device
-7
-6
-5
Units
LVCMOS25 Global Clock Input to Output
Delay using Output Flip-flop, 12 mA, Fast
Slew Rate, with DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard Adjustments, page 26.
Global Clock and OFF with DCM
T_ICKOFDCM
XC2VP2
1.55
1.59
1.62
ns
XC2VP4
1.58
1.61
1.65
ns
XC2VP7
1.63
1.68
1.72
ns
XC2VP20
1.68
1.74
1.79
ns
XC2VPX20
1.68
1.74
1.79
ns
XC2VP30
1.68
1.75
1.80
ns
XC2VP40
1.71
1.86
1.92
ns
XC2VP50
1.80
2.00
2.07
ns
XC2VP70
1.87
2.07
2.24
ns
XC2VPX70
1.87
2.07
2.24
ns
XC2VP100
N/A
2.38
2.45
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V_CC threshold with test setup shown in Figure 6. For other I/O standards, see Table 37.
3. DCM output jitter is already included in the timing calculation.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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