HD64F3048F16 Datasheet, PDF (96/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
T₁
T₂
φ
Address bus
Address
AS, RD, HWR, LWR
D₁₅ to D₀
High
High-impedance
Figure 2.16 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2.17 shows the on-chip supporting module access
timing. Figure 2.18 indicates the pin states.
φ
Address bus
Read
access
Internal read signal
Internal data bus
T₁ state
Bus cycle
T₂ state
T₃ state
Address
Read data
Write
access
Internal write signal
Internal data bus
Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
Rev. 3.00 Sep 27, 2006 page 68 of 872
REJ09B0325-0300