HD64F3048F16 Datasheet, PDF (224/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Refresh Controller
7.4 Interrupt Source
Compare match interrupts (CMI) can be generated when the refresh controller is used as an
interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of
RTMCSR.
7.5 Usage Notes
When using the DRAM or pseudo-static RAM refresh function, note the following points:
• With the refresh controller, if directly connected DRAM or PSRAM is disconnected*, the
P8₀/RFSH/IRQ₀ pin and the P8₁/CS₃/IRQ₁ pin may both become low-level outputs
simultaneously.
Note: * When the DRAM enable bit (DRAME) or PSRAM enable bit (PSRAME) in the
refresh control register (RFSHCR) is cleared to 0 after being set to 1.
Address bus
P8₀/RFSH/IRQ₀
P8₁/CS₃/IRQ₁
Area 3 start address
Figure 7.23 Operation when DRAM/PSRAM Connection Is Switched
• Refresh cycles are not executed while the bus is released, during software standby mode, and
when a bus cycle is greatly prolonged by insertion of wait states. When these conditions occur,
other means of refreshing are required.
• If refresh requests occur while the bus is released, the first request is held and one refresh cycle
is executed after the bus-released state ends. Figure 7.24 shows the bus cycles in this case.
Rev. 3.00 Sep 27, 2006 page 196 of 872
REJ09B0325-0300