HD64F3048F16 Datasheet, PDF (541/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Serial Communication Interface
Switching SCK Pin to Port Output Pin in Synchronous Mode
When the SCK pin is used as the serial clock output in synchronous mode, and is then switched to
its output port function at the end of transmission, a low level may be output for one half-cycle.
Half-cycle low-level output occurs when SCK is switched to its port function with the following
settings when DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1.
1. End of serial data transmission
2. TE bit = 0
3. C/A bit = 0 ... switchover to port output
4. Occurrence of low-level output (see figure 13.23)
Half-cycle low-level output
SCK/port
Data
Bit 6
TE
C/A
1. End of transmission
Bit 7
2. TE = 0
4. Low-level output
3. C/A = 0
CKE1
CKE0
Figure 13.23 Operation when Switching from SCK Pin to Port Pin
Rev. 3.00 Sep 27, 2006 page 513 of 872
REJ09B0325-0300