HD64F3048F16 Datasheet, PDF (243/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 7: DTE
0
1
Section 8 DMA Controller
Description
Data transfer is disabled (DTE is cleared to 0 when the specified number of
transfers have been completed)
(Initial value)
Data transfer is enabled
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6: DTSZ
0
1
Description
Byte-size transfer
Word-size transfer
(Initial value)
Bit 5—Source Address Increment/Decrement (SAID) and
Bit 4—Source Address Increment/Decrement Enable (SAIDE): These bits select whether the
source address register (MARA) is incremented, decremented, or held fixed during the data
transfer.
Bit 5: SAID
0
1
Bit 4: SAIDE
0
1
0
1
Description
MARA is held fixed
(Initial value)
MARA is incremented after each data transfer
• If DTSZ = 0, MARA is incremented by 1 after each
transfer
• If DTSZ = 1, MARA is incremented by 2 after each
transfer
MARA is held fixed
MARA is decremented after each data transfer
• If DTSZ = 0, MARA is decremented by 1 after each
transfer
• If DTSZ = 1, MARA is decremented by 2 after each
transfer
Rev. 3.00 Sep 27, 2006 page 215 of 872
REJ09B0325-0300