HD64F3048F16 Datasheet, PDF (123/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3: UE
0
1
Description
UI bit in CCR is used as interrupt mask bit
UI bit in CCR is used as user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2: NMIEG
0
1
Description
Interrupt is requested at falling edge of NMI input
Interrupt is requested at rising edge of NMI input
(Initial value)
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
Rev. 3.00 Sep 27, 2006 page 95 of 872
REJ09B0325-0300