HD64F3048F16 Datasheet, PDF (670/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Power-Down State
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7: SSBY
0
1
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms. See table 20.3.
If an external clock is used, select the setting so that the waiting time is 100 µs or more according
to the clock frequency.
Bit 6: STS2
0
1
Bit 5: STS1
0
1
0
1
Bit 4: STS0
0
1
0
1
0
1
0
1
Description
Waiting time = 8,192 states
Waiting time = 16,384 states
Waiting time = 32,768 states
Waiting time = 65,536 states
Waiting time = 131,072 states
Waiting time = 262,144 states
Waiting time = 1,024 states
Illegal setting
(Initial value)
Rev. 3.00 Sep 27, 2006 page 642 of 872
REJ09B0325-0300