HD64F3048F16 Datasheet, PDF (722/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 21 Electrical Characteristics
21.3.2 Refresh Controller Bus Timing
Refresh controller bus timing is shown as follows:
• DRAM bus timing
Figures 21.10 to 21.15 show the DRAM bus timing in each operating mode.
• PSRAM bus timing
Figures 21.16 and 21.17 show the pseudo-static RAM bus timing in each operating mode.
T₁
T₂
T₃
φ
t_AD
t_AD
A₉ to A₁
AS
CS₃ (RAS)
t_RAD1
t_AS1
RD (CAS)
HWR (UW),
LWR (LW )
(read)
HWR (UW),
LWR (LW )
(write)
t_RAH
t_ASD
t_AS1
t_RAD3
t_SD
t_CAS
t_RP
t_CRP
t_ASD
t_RAC
t_AA
t_CAC
t_SD
t_WDH
RFSH
D₁₅ to D₀
(read)
D₁₅ to D₀
(write)
t_WDS3
t_RDS
t_RDH
Figure 21.10 DRAM Bus Timing (Read/Write): Three-State Access
— 2WE Mode —
Rev. 3.00 Sep 27, 2006 page 694 of 872
REJ09B0325-0300